1. Field of the Invention
The present invention relates to a level conversion circuit converting the voltage amplitude of an input signal to a larger voltage amplitude, and a semiconductor device and a display unit employing the same.
2. Description of the Background Art
In recent years, a chip, referred to as a system-on-silicon chip, formed by loading a microprocessor or a memory on the same chip as a logic circuit is developed as an integrated circuit employing bulk silicon. Following such development, a technique of forming a number of types of circuits on a single chip with the finest possible design rules is now in the process of development.
However, the design rules vary with the types of the circuits, and hence circuits having different design rules must inevitably be integrated. Consequently, a plurality of circuits operating with different supply voltages are mixedly formed in a single chip. In this case, the voltages must be level-converted in an interface part between the different circuits.
Improvement of a high-speed property is attained by mixedly forming a plurality of circuits of different types on the same chip. Therefore, a level conversion circuit performing level conversion of voltages between the different circuits must also have high-speed operability.
Thin-film transistors of polycrystalline silicon are employed for a display device such as a liquid crystal display unit or an organic EL (electroluminescence) device. When provided on the same substrate as such a display device, the level conversion circuit is also formed by thin-film transistors of polycrystalline silicon.
In steps of fabricating transistors, device characteristics such as threshold voltages vary. Particularly in thin-film transistors of polycrystalline silicon, variations of device characteristics such as threshold voltages are extremely large. Thus, awaited is a level conversion circuit capable of reliably operating also when device characteristics such as threshold voltages of thin-film transistors vary.
Such a display device requires a level conversion circuit capable of operating at a high speed also when an input signal having a small amplitude is supplied in view of reduction of power consumption and improvement in definition.
FIG. 45 is a circuit diagram showing a first exemplary conventional level conversion circuit 800.
The level conversion circuit 800 shown in FIG. 45 includes two p-channel MOSFETs (metal-oxide semiconductor field-effect transistors) 801 and 802 and two n-channel MOSFETs 803 and 804.
The p-channel MOSFETs 801 and 802 are connected between a power supply terminal receiving a supply potential VDD and output nodes N11 and N12 respectively, while the n-channel MOSFETs 803 and 804 are connected between the output nodes N11 and N12 and a ground terminal respectively. The gates of the p-channel MOSFETs 801 and 802 are cross-coupled to the output nodes N12 and N11 respectively. The gates of the n-channel MOSFETs 803 and 804 are supplied with mutually complementarily changing input signals CLK1 and CLK2 respectively.
When the input signal CLK1 goes high and the input signal CLK2 goes low, the n-channel MOSFET 803 is turned on and the n-channel MOSFET 804 is turned off. Thus, the p-channel MOSFET 802 is turned on and the p-channel MOSFET 801 is turned off. Consequently, an output potential Vout of the output node N12 increases. When the input signal CLK1 goes low and the input signal CLK2 goes high, on the other hand, the output potential Vout of the output node N12 decreases.
In this case, the voltage amplitudes of the input signals CLK1 and CLK2 must be larger than the threshold voltages Vtn of the n-channel MOSFETs 803 and 804, in order to turn on the n-channel MOSFETs 803 and 804.
Therefore, the level conversion circuit 800 shown in FIG. 45 is employed when the voltage ratio between input and output signals is small.
For example, this level conversion circuit 800 is effective when converting a 3 V-system signal to a 5 V-system signal, converting a 2.5 V-system signal to a 3 V-system signal or converting a 1.8 V-system signal to a 2.5 V- or 3.3 V-system signal.
FIG. 46 is a circuit diagram showing a second exemplary conventional level conversion circuit 810.
The level conversion circuit 810 shown in FIG. 46 includes a bias circuit 811, a p-channel MOSFET 812 and an n-channel MOSFET 813.
The p-channel MOSFET 812 is connected between a power supply terminal receiving a supply potential VDD and an output node N13, while the n-channel MOSFET 813 is connected between the output node N13 and another power supply terminal receiving a prescribed potential VEE. An input signal CLK is supplied to the gate of the p-channel MOSFET 812 and the bias circuit 811. The bias circuit 811 supplies the input signal CLK to the gate of the n-channel MOSFET 813 while shifting the central level thereof.
When the input signal CLK goes high, the p-channel MOSFET 812 is turned off and the n-channel MOSFET 813 is turned on. Thus, an output potential Vout of the output node N13 decreases. When the input signal CLK goes low, on the other hand, the p-channel MOSFET 812 is turned on and the n-channel MOSFET 813 is turned off. Thus, the output potential Vout of the output node N13 increases.
In this case, the bias circuit 811 shifts the central level of the input signal CLK, and hence the level conversion circuit 810 operates also when the voltage amplitude of the input signal CLK is smaller than the threshold voltage Vtn of the n-channel MOSFET 813.
FIG. 47 is a circuit diagram showing a third exemplary conventional level conversion circuit 820.
The level conversion circuit 820 shown in FIG. 47 includes a clamping circuit 821 and a current mirror amplifier 822.
The current mirror amplifier 822 includes two p-channel MOSFETs 831 and 832 and two n-channel MOSFETs 833 and 834. The p-channel MOSFETs 831 and 832 are connected between power supply terminals receiving a supply potential VDD and output nodes N14 and N15 respectively. The n-channel MOSFETs 833 and 834 are connected between the output nodes N14 and N15 and ground terminals respectively. The gates of the p-channel MOSFETs 831 and 832 are connected to the output node N14. The clamping circuit 821 supplies mutually complementarily changing input signals CLK1 and CLK2 to the gates of the n-channel MOSFETs 833 and 834 while shifting the central levels thereof.
When the input signal CLK1 goes high and the input signal CLK2 goes low, the n-channel MOSFET 833 is turned on and the n-channel MOSFET 834 is turned off. Thus, the p-channel MOSFETs 831 and 832 are turned on. Consequently, an output potential Vout of the output node N15 increases. When the input signal CLK1 goes low and the input signal CLK2 goes high, on the other hand, the output potential Vout of the output node N15 decreases.
In this case, the clamping circuit 821 shifts the central levels of the input signals CLK1 and CLK2, and hence the level conversion circuit 820 can operate also when the voltage amplitudes of the input signals CLK1 and CLK2 are smaller than the threshold voltages Vtn of the n-channel MOSFETs 833 and 834.
FIG. 48 is a circuit diagram showing a fourth exemplary conventional level conversion circuit 840.
The level conversion circuit 840 shown in FIG. 48 includes a clamping circuit 841 and a PMOS cross-coupled amplifier 842.
The PMOS cross-coupled amplifier 842 includes two p-channel MOSFETs 851 and 852 and two n-channel MOSFETs 853 and 854. The p-channel MOSFETs 851 and 852 are connected between power supply terminals receiving a supply potential VDD and output nodes N16 and N17 respectively, while the n-channel MOSFETs 853 and 854 are connected between the output nodes N16 and N17 and ground terminals respectively. The gates of the p-channel MOSFETs 851 and 852 are cross-coupled to the output nodes N17 and N16 respectively. The clamping circuit 841 supplies mutually complementarily changing input signals CLK1 and CLK2 to the gates of the n-channel MOSFETs 853 and 854 respectively while shifting the central levels thereof.
When the input signal CLK1 goes high and the input signal CLK2 goes low, the n-channel MOSFET 853 is turned on and the n-channel MOSFET 854 is turned off. Thus, the p-channel MOSFET 851 is turned off and the p-channel MOSFET 852 is turned on. Consequently, an output potential Vout of the output node N17 increases. When the input signal CLK1 goes low and the input signal CLK2 goes high, on the other hand, the output potential Vout of the output node N17 decreases.
In this case, the clamping circuit 841 shifts the central levels of the input signals CLK1 and CLK2, and hence the level conversion circuit 840 can operate also when the voltage amplitudes of the input signals CLK1 and CLK2 are smaller than the threshold voltages Vtn of the n-channel MOSFETs 853 and 854.
As hereinabove described, the level conversion circuit 800 shown in FIG. 45 cannot operate when the voltage amplitudes of the input signals CLK1 and CLK2 are smaller than the threshold voltages Vtn of the n-channel MOSFETs 803 and 804.
Referring to FIG. 46, on the other hand, the bias circuit 811 shifts the central level of the input signal CLK, and hence the level conversion circuit 810 can operate also when the voltage amplitude of the input signal CLK is smaller than the threshold voltage Vtn of the n-channel MOSFET 813.
Referring to FIGS. 47 and 48, the clamping circuits 821 and 841 similarly shift the central levels of the input signals CLK1 and CLK2, and hence the level conversion circuits 820 and 840 can operate also when the voltage amplitudes of the input signals CLK1 and CLK2 are smaller than the threshold voltages Vtn of the n-channel MOSFETs 833, 834, 853 and 854.
However, the level conversion circuits 810, 820 and 840 shown in FIGS. 46 to 48 may not operate when the threshold voltages Vtn of the n-channel MOSFETs 833, 834, 853 and 854 remarkably deviate from design values due to variations in fabrication steps.
In any of the level conversion circuits 800, 810, 820 and 840 shown in FIGS. 45 to 48, further, the duty ratio of an output waveform deviates from a prescribed design value when the threshold voltages Vtp and Vtn of the p-channel and n-channel MOSFETs irregularly vary in fabrication steps, e.g., when the threshold voltage(s) Vtn of the n-channel MOSFET(s) increases and the threshold voltage(s) Vtp of the p-channel MOSFET(s) increases or vice versa.
Particularly when employing the level conversion circuit for forming a clock signal for a display device such as a liquid crystal display unit or an organic EL device, the duty ratio of the clock signal must be set to 50%. When the duty ratio of the clock signal deviates from 50% due to irregular change of the threshold voltages Vtn and Vtp of the n-channel and p-channel MOSFETs of the level conversion circuit, turn-on and turn-off times of pixels vary in the display device.
In the level conversion circuit 800 shown in FIG. 45, the p-channel MOSFETs 801 and 802 extract gate charges from each other when ON and OFF states of the n-channel MOSFETs 803 and 804 are inverted. Therefore, it takes time to invert the level of the output potential Vout, and the operating speed cannot be increased.
Particularly when the p-channel MOSFETs 801 and 802 are formed by transistors such as thin-film transistors of polycrystalline silicon having small drivability, the time required for inverting the level of the output potential Vout is further increased.
When the level of the output potential Vout is inverted, a through current flows from the power supply terminal to the ground terminal through a path of the p-channel MOSFET 801 and the n-channel MOSFET 803 or that of the p-channel MOSFET 802 and the n-channel MOSFET 804. Particularly when it takes time to invert the level of the output potential Vout, the flowing time of the through current is increased to increase power consumption.
The bias circuit 811 of the level conversion circuit 810 shown in FIG. 46 feeds a current to a resistive element thereby forming potential difference between the input signal CLK and an output signal. In this case, it takes time to set the potential difference between the input signal CLK and the output signal, to hinder high-speed operation. Further, a large layout area is required for forming the resistive element. In addition, the current regularly flows to the resistive element, to increase power consumption. Further, high-speed operation cannot be attained and hence the through current is increased in the p-channel MOSFET 810 and the n-channel MOSFET 813 of the output stage.
The clamping circuits 821 and 841 of the level conversion circuits 820 and 840 shown in FIGS. 47 and 48 are also inhibited from high-speed operation, require large layout areas and increase power consumption, similarly to the bias circuit 811 of the level conversion circuit 810 shown in FIG. 46.
An object of the present invention is to provide a level conversion circuit capable of reliably operating also when the threshold voltage of a transistor deviates from a design value due to variations in fabrication steps, while enabling high-speed operation, reduction of power consumption and area reduction.
Another object of the present invention is to provide a semiconductor device employing a level conversion circuit capable of reliably operating also when the threshold voltage of a transistor deviates from a design value due to variations in fabrication steps, while enabling high-speed operation, reduction of power consumption and area reduction.
Still another object of the present invention is to provide a display unit employing a level conversion circuit capable of reliably operating also when the threshold voltage of a transistor deviates from a design value due to dispersion in fabrication steps, while enabling high-speed operation, reduction of power consumption and area reduction.
A level conversion circuit according to an aspect of the present invention comprises a first transistor connected between a first node receiving a first potential and an output node, a second transistor connected between a second node receiving a second potential different from the first potential and the output node, and a control part receiving a first input signal and bringing both of the first and second transistors into ON states while controlling the degrees of the ON states of the first and second transistors respectively in response to the level of the first input signal.
In the level conversion circuit, the control part brings both of the first and second transistors into ON states while controlling the degrees of the ON states of the first and second transistors respectively in response to the level of the first input signal. Thus, the potential of the output node increases or decreases in response to the level of the first input signal.
In this case, the degrees of the ON states of the first and second transistors which are regularly on are controlled to change the potential of the output node, whereby the level conversion circuit can operate also when the voltage amplitude of the first input signal is smaller than the threshold voltages of the first and second transistors. Also when the threshold voltages of the first and second transistors remarkably deviate from design values, further, the duty ratio of potential change of the output node correctly corresponds to the duty ratio of the first input signal. Thus, the level conversion circuit can reliably operate also when the threshold voltages of the transistors deviate from the design values due to variations in fabrication steps.
The ON states of the first and second transistors which are regularly on are controlled to change the potential of the output node, whereby the level conversion circuit can operate at a high speed. Further, a transition period of the level of the potential of the output node is shortened due to the enabled high-speed operation, thereby reducing a flowing period of a through current. Thus, power consumption can be reduced.
No level-shifting circuit is required also when the first input signal has a small voltage amplitude, whereby the area can be reduced.
The first input signal may change with a voltage amplitude smaller than the difference between the first potential and the second potential.
In this case, the potential of the output node changes with a voltage amplitude larger than the voltage amplitude of the first input signal.
The first input signal may change to a first level and a second level, the first transistor may be a first conductive channel field-effect transistor and the second transistor may be a second conductive channel field-effect transistor, while the control part may set the gate potential of the first conductive channel field-effect transistor and the gate potential of the second conductive channel field-effect transistor in response to the first and second levels of the first input signal so that the absolute value of the difference between the first potential and the gate potential of the first conductive channel field-effect transistor exceeds the absolute value of the threshold voltage of the first conductive channel field-effect transistor and the absolute value of the difference between the second potential and the gate potential of the second conductive channel field-effect transistor exceeds the absolute value of the threshold voltage of the second conductive channel field-effect transistor.
In this case, the absolute value of the difference between the first potential and the gate potential of the first conductive channel field-effect transistor exceeds the absolute value of the threshold voltage of the first conductive channel field-effect transistor, whereby the first conductive channel field-effect transistor is regularly on. Further, the absolute value of the difference between the second potential and the gate potential of the second conductive channel field-effect transistor exceeds the absolute value of the threshold voltage of the second conductive channel field-effect transistor, whereby the second conductive channel field-effect transistor is regularly on.
Thus, the level conversion circuit can reliably operate also when the threshold voltages of the transistors deviate from design values, while enabling high-speed operation, reduction of power consumption and area reduction.
The first potential may be a positive potential, and the second potential may be a positive potential lower than the first potential, a ground potential or a negative potential.
In this case, the first and second transistors are regularly on and hence a current flows from the first node to the second node through the first and second transistors.
The second potential may be a second input signal changing to a first level and a second level complementarily with the first input signal.
In this case, the first and second levels of the first and second input signals are lower than the first potential, the second input signal reaches the second level when the first input signal is at the first level, and the second input signal reaches the first level when the first input signal is at the second level.
The first conductive channel field-effect transistor may be a first p-channel field-effect transistor having a first threshold voltage, the second conductive channel field-effect transistor may be a first n-channel field-effect transistor having a second threshold voltage, and the control part may set the gate potential of the first p-channel field-effect transistor within a range lowering from the first potential by at least the absolute value of the first threshold voltage while setting the gate potential of the first n-channel field-effect transistor within a range rising from the second potential by at least the absolute value of the second threshold voltage.
In this case, the gate potential of the first p-channel field-effect transistor is set within the range lowering from the first potential by at least the absolute value of the first threshold voltage, whereby the first p-channel field-effect transistor is regularly on. The first p-channel field-effect transistor is weakly turned on when the gate potential thereof is at a high level within the aforementioned range, while the first p-channel field-effect transistor is strongly turned on when the gate potential thereof is at a low level within the aforementioned range.
The gate potential of the first n-channel field-effect transistor is set within the range rising from the second potential by at least the absolute value of the second threshold voltage, whereby the first n-channel field-effect transistor is regularly on. The first n-channel field-effect transistor is weakly turned on when the gate potential thereof at a low level within the aforementioned range, while the first n-channel field-effect transistor is strongly turned on when the gate potential thereof is at a high level within the aforementioned range.
The control part may include a second p-channel field-effect transistor, a second n-channel field-effect transistor and a control circuit, the source of the second p-channel field-effect transistor may receive the first potential, the gate and the drain of the second p-channel field-effect transistor may be connected to the gate of the first p-channel field-effect transistor, the source of the second n-channel field-effect transistor may receive the first input signal or the second potential, the gate and the drain of the second n-channel field-effect transistor may be connected to the gate of the first n-channel field-effect transistor, and the control circuit may control the potential of the drain of the second p-channel field-effect transistor and the potential of the drain of the second n-channel field-effect transistor in response to the level of the first input signal.
In this case, the second p-channel field-effect transistor sets the gate potential of the first p-channel field-effect transistor within the range lowering from the first potential by at least the absolute value of the first threshold voltage. Further, the second n-channel field-effect transistor sets the gate potential of the first n-channel field-effect transistor within the range rising from the second potential by at least the absolute value of the second threshold voltage. In addition, the control circuit controls the gate potential of the first p-channel field-effect transistor within the aforementioned range while controlling the gate potential of the first n-channel field-effect transistor within the aforementioned range.
The control circuit may include first and second load elements, an end of the first load element may receive the first input signal, the other end of the first load element may be connected to the gate of the first p-channel field-effect transistor, an end of the second load element may receive the first potential, and the other end of the second load element may be connected to the gate of the first n-channel field-effect transistor.
In this case, the first load element controls the gate potential of the first p-channel field-effect transistor while the second load element controls the gate potential of the first n-channel field-effect transistor in response to the level of the first input signal.
According to this structure, the level conversion circuit is formed by six elements, whereby the area is reduced.
Each of the first and second load elements may be a field-effect transistor or a resistive element.
In this case, the gate potentials of the first p-channel field-effect transistor and the first n-channel field-effect transistor are controlled by field-effect transistors or resistive elements.
The control part may further include a third p-channel field-effect transistor and a third n-channel field-effect transistor, the source, the gate and the drain of the third p-channel field-effect transistor may be connected to the source of the second p-channel field-effect transistor, the output node and the drain of the second p-channel field-effect transistor respectively, and the source, the gate and the drain of the third n-channel field-effect transistor may be connected to the source of the second n-channel field-effect transistor, the output node and the drain of the second n-channel field-effect transistor respectively.
In this case, the first p-channel field-effect transistor and the first n-channel field-effect transistor can be reliably turned on also when the difference between the first and second potentials is small. Thus, low-voltage driving is enabled.
The control part may include a second n-channel field-effect transistor and a control circuit, the source of the second n-channel field-effect transistor may receive the first input signal or the second potential, the gate and the drain of the second n-channel field-effect transistor may be connected to the gate of the first n-channel field-effect transistor, and the control circuit may control the potential of the gate of the first n-channel field-effect transistor and the potential of the drain of the second n-channel field-effect transistor in response to the level of the first input signal.
In this case, the control circuit sets the gate potential of the first p-channel field-effect transistor within the range lowering from the first potential by at least the absolute vale of the first threshold voltage. Further, the second n-channel field-effect transistor sets the gate potential of the first n-channel field-effect transistor within the range rising from the second potential by at least the absolute value of the second threshold voltage. In addition, the control circuit controls the gate potential of the first p-channel field-effect transistor within the aforementioned range, and controls the gate potential of the first n-channel field-effect transistor within the aforementioned range.
The control circuit may include first, second and third load elements, an end of the first load element may receive the first potential, the other end of the first load element may be connected to the gate of the first p-channel field-effect transistor, an end of the second load element may receive the first input signal or the second potential, the other end of the second load element may be connected to the gate of the first p-channel field-effect transistor, an end of the third load element may receive the first potential, and the other end of the third load element may be connected to the gate of the first n-channel field-effect transistor.
In this case, the first and second load elements control the gate potential of the first p-channel field-effect transistor and the third load element controls the gate potential of the first n-channel field-effect transistor in response to the level of the first input signal.
According to this structure, the level conversion circuit is formed by six elements, whereby the area is reduced.
Each of the first, second and third load elements may be a field-effect transistor or a resistive element.
In this case, the gate potentials of the first p-channel field-effect transistor and the first n-channel field-effect transistor are controlled by field-effect transistors or resistive elements.
The level conversion circuit may further comprise cutoff circuit cutting off a current path reaching the second node from the first node through the first and second transistors in a transition period between a first level and a second level of the first input signal.
In this case, no current flows to the first and second transistors in the transition period between the first and second levels of the first input signal, whereby increase of power consumption caused by a through current is prevented. Therefore, power consumption is further reduced.
The first transistor, the second transistor and the control part may be made of a single-crystalline, polycrystalline or amorphous semiconductor on an insulating substrate.
In this case, the level conversion circuit is formed by an SOI (silicon on insulator) device.
A semiconductor device according to another aspect of the present invention comprises a prescribed circuit and a level conversion circuit connected to the prescribed circuit, and the level conversion circuit comprises a first transistor connected between a first node receiving a first potential and an output node, a second transistor connected between a second node receiving a second potential different from the first potential and the output node, and a control part receiving a first input signal and bringing both of the first and second transistors into ON states while controlling the degrees of the ON states of the first and second transistors respectively in response to the level of the first input signal.
The prescribed circuit may include a plurality of logic circuits operating with different supply voltages, and the level conversion circuit may be connected between the plurality of logic circuits.
In this case, reliable operation as well as high-speed operation, reduction of power consumption and area reduction are enabled in the semiconductor device comprising the plurality of logic circuits operating with different supply voltages, also when the variations of the threshold voltages of the transistors are large in fabrication steps.
The prescribed circuit may include an internal circuit provided on a chip and an external circuit provided outside the chip, and the level conversion circuit may be connected between the internal circuit and the external circuit.
In this case, reliable operation as well as high-speed operation, reduction of power consumption and area reduction are enabled in the semiconductor device comprising the internal circuit provided on the chip and the external circuit provided outside the chip, also when the variations of the threshold voltages of the transistors are large in fabrication steps.
The prescribed circuit may include a semiconductor memory provided on a chip and a logic circuit provided on the chip, and the level conversion circuit may be connected between the semiconductor memory and the logic circuit on the chip.
In this case, reliable operation as well as high-speed operation, reduction of power consumption and area reduction are enabled in the semiconductor device comprising the semiconductor memory and the logic circuit mixedly provided on the chip, also when the variations of the threshold voltages of the transistors are large in fabrication steps.
The prescribed circuit may include a plurality of sensors, a plurality of selection transistors for selecting any of the plurality of sensors and a peripheral circuit driving the plurality of sensors through the plurality of selection transistors, and the level conversion circuit may level-convert a prescribed signal and supply the level-converted prescribed signal to the peripheral circuit.
In this case, reliable operation as well as high-speed operation, reduction of power consumption and area reduction are enabled in the semiconductor device having the plurality of selection transistors and the level conversion circuit, also when the variations of the threshold voltages of the transistors are large in fabrication steps.
A display unit according to still another aspect of the present invention comprises a plurality of display elements, a plurality of selection transistors for selecting any of the plurality of display elements, a peripheral circuit driving the plurality of display elements through the plurality of selection transistors, and a level conversion circuit level-converting a prescribed signal and supplying the level-converted signal to the peripheral circuit, and the level conversion circuit comprises a first transistor connected between a first node receiving a first potential and an output node, a second transistor connected between a second node receiving a second potential different from the first potential and the output node, and a control part receiving a first input signal and bringing both of the first and second transistors into ON states while controlling the degrees of the ON states of the first and second transistors respectively in response to the level of the first input signal.
In this case, reliable operation as well as high-speed operation, reduction of power consumption, area reduction and improvement in definition are enabled in the display unit having the plurality of selection transistors and the level conversion circuit, also when the variations of the threshold voltages of the transistors are large in fabrication steps.
The plurality of display elements may be liquid crystal elements, and the plurality of liquid crystal elements, the plurality of selection transistors, the peripheral circuit and the level conversion circuit may be formed on an insulating substrate.
In this case, a liquid crystal display unit capable of reliable operation as well as high-speed operation, reduction of power consumption, area reduction and improvement in definition is implemented also when the variations of the threshold voltages of the transistors are large in fabrication steps.
The plurality of display elements may be organic electroluminescence elements, and the plurality of organic electroluminescence elements, the plurality of selection transistors, the peripheral circuit and the level conversion circuit may be formed on an insulating substrate.
In this case, an organic electroluminescence device capable of reliable operation as well as high-speed operation, reduction of power consumption, area reduction and improvement in definition is implemented also when the variations of the threshold voltages of the transistors are large in fabrication steps.
The plurality of selection transistors and the first and second transistors of the level conversion circuit may be formed by thin-film transistors.
In this case, a display unit capable of reliable operation as well as high-speed operation, reduction of power consumption, area reduction and improvement in definition is implemented also when the variations of the threshold voltages of the thin-film transistors are large in fabrication steps.